Chromite M Soc Manual

Welcome to the ChromiteM SoCs documentation. The source code of the SoC is available at: https://gitlab.incoresemi.com/fpga_ports/chromitem_soc

Note

Proprietary Notice

Copyright (c) 2020, InCore Semiconductors Pvt. Ltd.

Information in this document is provided “as is” with faults, if any.

InCore expressly disclaims all warranties, representations, and conditions of any kind, whether express or implied, including, but not limited to, the implied warranties or conditions of merchantability, fitness for a particular purpose and non-infringement.

InCore does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, special, exemplary, or consequential damages.

InCore reserves the right to make changes without further notice to any products herein.

• 1. Introduction
  • 1.1. Overview
• 2. Memory Map
• 3. Getting Started
  • 3.1. Requirements
  • 3.2. Building the FPGA Target
  • 3.3. Debug Programs
  • 3.4. Flash Program
  • 3.5. Simulating the SoC
• 4. Supported FPGAs
  • 4.1. ARTY 100t
• 5. OS Ports
  • 5.1. Zephyr
• 6. Core Pipeline
  • 6.1. PC Gen Stage
  • 6.2. Instruction Fetch Stage (IFS)
  • 6.3. Decode Stage
  • 6.4. Execution Stage
  • 6.5. Memory Stage
  • 6.6. Write Back Stage
  • 6.7. Handling Re-directions
  • 6.8. Instruction Latencies
• 7. Modes of Operation
• 8. Custom CSRs
  • 8.1. custom control (0x800)
  • 8.2. dtvec (0x7c0)
  • 8.3. denable (0x7c1)
  • 8.4. mhpminterrupten (0x7c2)
• 9. Physical Memory Protection (PMP)
  • 9.1. PMP Granularity
• 10. Performance Monitors
  • 10.1. Need for Daisy Chaining
  • 10.2. List of Events for
  • 10.3. Interrupts from Counters
• 11. L1 Cache Subsytem
  • 11.1. Cache Feature List
  • 11.2. Theory of Operation
• 12. Interrupts
  • 12.1. Interrupt Concepts
  • 12.2. Interrupt Entry and Exit
  • 12.3. Interrupt Control Status Registers
  • 12.4. Interrupt Priorities
• 13. Debug
  • 13.1. Hart Debug CSRs
  • 13.2. Debug Memory Map
• 14. Debug Interface
  • 14.1. Resetting Logic
  • 14.2. JTAG Clocking
  • 14.3. JTAG Debug Commands
  • 14.4. Using the BSCANE2 primitive
• 15. Boot Config
• 16. General Purpose Input Output Controller
  • 16.1. IP Details and Available Configuration
  • 16.2. GPIO Instance Details
  • 16.3. Register Map
  • 16.4. INPUT_VAL Register
  • 16.5. INPUT_ENABLE Register
  • 16.6. OUTPUT_VAL Register
  • 16.7. OUTPUT_EN Register
  • 16.8. PULLUP_EN Register
  • 16.9. DRIVE_0 Register
  • 16.10. RISE_IE Register
  • 16.11. RISE_IP Register
  • 16.12. FALL_IE Register
  • 16.13. FALL_IP Register
  • 16.14. HIGH_IE Register
  • 16.15. HIGH_IP Register
  • 16.16. LOW_IE Register
  • 16.17. LOW_IP Register
  • 16.18. SET_OUT Register
  • 16.19. CLR_OUT Register
  • 16.20. XOR_OUT Register
  • 16.21. DRIVE_1 Register
  • 16.22. DRIVE_2 Register
  • 16.23. Input/Output Values
  • 16.24. Interrupts
  • 16.25. Output Logic Locking
  • 16.26. IO and Sideband Signals
• 17. Core Local Interrupt (CLINT)
  • 17.1. IP Details and Available Configuration
  • 17.2. CLINT Instance Details
  • 17.3. Register Map
  • 17.4. MSIP Register
  • 17.5. MTIMECMP Register
  • 17.6. MTIME Register
  • 17.7. IO and Sideband Signals
• 18. Platform Level Interrupt Controller (PLIC)
  • 18.1. IP Details and Available Configuration
  • 18.2. PLIC Instance Details
  • 18.3. Register Map
  • 18.4. PLIC Interrupt Priorities
  • 18.5. PLIC Interrupt Pending Bits
  • 18.6. Interrupt Enables
  • 18.7. Interrupt Thresholds
  • 18.8. Interrupt Claim Process
  • 18.9. Interrupt Completion
  • 18.10. IO and Sideband Signals
  • 18.11. PLIC Interrupt Mapping
• 19. Universal Asynchronous Receiver/Transmitter (UART)
  • 19.1. IP Details and Available Configuration
  • 19.2. UART Instance Details
  • 19.3. UART Features
  • 19.4. Register Map
  • 19.5. BAUD Register
  • 19.6. TX_DATA Register
  • 19.7. RX_DATA Register
  • 19.8. STATUS Register
  • 19.9. CONTROL Register
  • 19.10. STATUS_CLEAR Register
  • 19.11. INTERRUPT_EN Register
  • 19.12. IO and Sideband Signals
• 20. Pulse Width Modulation (PWM) Module
  • 20.1. IP Details and Available Configuration
  • 20.2. PWM Instance Details
  • 20.3. PWM Features
  • 20.4. Register Map
  • 20.5. CLOCK Register
  • 20.6. CONTROL_STATUS Register
  • 20.7. PERIOD Register
  • 20.8. DUTY CYCLE Register
  • 20.9. DEADBAND DELAY Register
  • 20.10. IO and Sideband Signals
  • 20.11. Peripheral Usage
• 21. Serial Peripheral Interface (SPI) Module
  • 21.1. IP Details and Available Configuration
  • 21.2. SPI Instance Details
  • 21.3. SPI Features
  • 21.4. Register Map
  • 21.5. SPI_CR1 Register
  • 21.6. SPI_CR2 Register
  • 21.7. SPI_EN Register
  • 21.8. SPI_SR Register
  • 21.9. TXR Register
  • 21.10. RXR Register
  • 21.11. RX_CRC Register
  • 21.12. TX_CRC Register
  • 21.13. SPI_DR Register
  • 21.14. SPI_PSCR Register
  • 21.15. SPI_CRCPR Register
  • 21.16. SPI_CRCINOUT Register
  • 21.17. IO and Sideband Signals
  • 21.18. Usage of SPI Module
• 22. QUAD Serial Peripheral Interface (QSPI) Module
  • 22.1. IP Details and Available Configuration
  • 22.2. QSPI Instance Details
  • 22.3. QSPI Features
  • 22.4. Register Map
  • 22.5. QUADSPI_CR Register
  • 22.6. QUADSPI_DCR Register
  • 22.7. QUADSPI_SR Register
  • 22.8. QUADSPI_FCR Register
  • 22.9. QUADSPI_DLR Register
  • 22.10. QUADSPI_CCR Register
  • 22.11. QUADSPI_AR Register
  • 22.12. QUADSPI_ABR Register
  • 22.13. QUADSPI_DR Register
  • 22.14. QUADSPI_PSMKR Register
  • 22.15. QUADSPI_PSMAR Register
  • 22.16. QUADSPI_PIR Register
  • 22.17. QUADSPI_LPTR Register
  • 22.18. IO and Sideband Signals
  • 22.19. Direct Memory Region
• 23. Licensing and Support